1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. The present invention relates to, e.g., a fin MOS transistor.
2. Description of the Related Art
Recent microfabrication of semiconductor devices is striking. However, along with the microfabrication, the performance of a planar MOS transistor cannot improve anymore because of the physical limit. To break the limit of the planar MOS transistor, a fin MOS transistor (double-gate MOS transistor) has been proposed. A fin MOS transistor is described in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 8-139325.
FIG. 1 is a sectional view of a fin MOS transistor described in Jpn. Pat. Appln. KOKAI Publication No. 8-139325. As shown in FIG. 1, a fin-shaped semiconductor layer (channel region) 120 is formed on an element region AA surrounded by an insulating film 110 formed in a semiconductor substrate (well region) 100. A source layer 130 and drain layer 140 are formed on the well region 100 to oppose each other via the channel region 120. A gate electrode 150 is formed on the upper surface of the channel region 120.
In the fin MOS transistor having the above structure, the current supply capability can be improved, as compared to a planar MOS transistor. In addition, the gate width can be further decreased. The gate electrode 150 surrounds the channel region 120. Hence, a leakage current that flows through the channel region 120 can easily be controlled, and the reliability of the MOS transistor can be increased.
However, even the conventional fin MOS transistor cannot solve all problems related to leakage current control. As described above, a fin MOS transistor can easily control a leakage current that flows through the channel region 120. However, it is difficult to control a leakage current that flows through the well region 100, as shown in FIG. 1. This is because a current that flows through the well region 100 is poorly controlled by the gate electrode 150. To solve this problem, for example, the impurity concentration in the well region 100 under the channel region 120 is increased. However, this measure causes a degradation in performance by, e.g., increasing the capacitance between the well region 100 and the source layer 130 and drain layer 140. As described above, the conventional fin MOS transistor has the same problem as that of a planar MOS transistor.